1. Field of the Invention
The present invention relates to phase locked loops (PLLs).
2. State of the Art
Practically all modem signal generators and radio communications equipment make widespread use of PLLs. A known PLL is shown in FIG. 1. A reference frequency fin is applied to a phase or phase/frequency detector, to which is also applied a feedback signal derived from an output frequency signal fout of the PLL. The detector produces an error signal, which is filtered by a loop filter. An output signal of the loop filter is applied to a voltage-controlled oscillator (VCO), which produces the output frequency signal fout. Commonly, a programmable divide-by-N counter divides down the output frequency signal fout to produce a lower frequency signal that is then applied to the detector. In this manner, an output frequency signal can be generated that is some multiple of the reference frequency. Such divide-by-N counters are typically realized in CMOS.
At very high frequencies (such as those used in cellular radiotelephones), however, the speed capability of even the fastest CMOS circuit is quickly exceeded. In this instance, a dual-modulus prescaler is commonly used in which the difference between one divide modulus (P) and the other divide modulus (P+1) is one. In such an arrangement, shown in FIG. 2, a high-speed (e.g., ECL) dual-modulus counter is followed by a lower-speed (e.g., CMOS) programmable counter. The lower-speed counter controls which modulus of the dual-modulus prescaler is active at a given time via a modulus control signal MC. The use of multiple moduli enables a full range of effective divisors to be obtained.
One construction of such a circuit is shown in FIG. 3, in which the dual-modulus counter is followed by a pair of lower-speed (e.g., CMOS) programmable counters. In the circuit of FIG. 3, the reference and output frequencies are related as follows:
                              f          out                =                ⁢                  N          ·                      f            in                                                  =                ⁢                              (                          QP              +              R                        )                    ⁢                      f            in                                                  =                ⁢                              (                                                            (                                      Q                    -                    R                                    )                                ⁢                P                            +                              R                ⁡                                  (                                      P                    +                    1                                    )                                                      )                    ⁢                      f            in                              where Q is the quotient of the integer division N/P and R is the remainder of the integer division N/P. The value Q is used to preset a “tens” counter (so-called because its effect is multiplied by the modulus P) and R is used to preset a “ones” counter (the effect of which is not multiplied by the modulus). The value Q must be greater than or equal to the value R. With this restriction, the minimum division ratio achievable to guarantee continuous coverage of the possible integer divisors N using such a circuit is, in general, P(P−1).
Assume, for example, that a 10/11 dual-modulus prescaler (P=10) is used and that a desired output frequency is 197 times the reference frequency. Using the foregoing formula, Q might be 19 and R might be 7. (Note that R<P always.) These values are preset into the respective counters. With a non-zero value loaded into the R counter, the dual-modulus prescaler is set to divide by P+1 at the start of the cycle. (The period of the cycle is given by the reciprocal of the reference frequency.) The output from the dual-modulus prescaler clocks both counters. When the R counter reaches zero, it ceases counting and sets the dual-modulus prescaler to divide by P. Only the Q counter is then clocked. Such a cycle is illustrated in FIG. 4. When the Q counter reaches zero, the initial values are again loaded into the counters and the next cycle begins.
In such a circuit, the modulus control signal for controlling the dual-modulus prescaler can generate considerable noise within the frequency band of the reference signal, since the period of this modulus control signal is equal to the period of the PLL reference signal. Various filtering strategies have been used to attack this problem. An effective, low-cost solution to this problem remains a long-standing need.